Summer is in full blow in the northern hemisphere, and, I think, particularly so in the Caribbean. Family commitments involving plenty of food and the beach, among less glamorous stuff, have kept me silent over here for almost two months now. This is just a short note to let you all know that I’ve been awarded a research grant from INTEC to work on architecture description languages (ADLs) as tools to assist high-level electronics design. Read on for some details.
Electronic engineers carry out what I’ll call low-level electronic design – building new chips, or ASICs, with very sophisticated tools, including FPGAs and advanced software known as hardware description languages (HDLs), of which Verilog and VHDL are two of the most known and used. These languages allow engineers to specify, simulate and validate their hardware design over FPGAs before committing to actual chip prototyping and mass production.
Increasingly, hobbyists, and not only engineers, are carrying out what I’ll call high-level electronic design – not creating new chips, but composing designs out of existing chips and other passive and active components. Even for engineers, high-level design is devoid of the assistance available for low-level design. Connected a 3.3-volt sensor to a 5-volt line? Hello, blue smoke. Chose an MCU with insufficient RAM or general-purpose input/output pins (GPIOs) to read or drive all other components? Figure out the hard way during assembly. I am not aware of tools that provide assistance at this level.
There are architecture description languages (ADLs) that mix hardware and software concerns, such as AADL, but I perceive they model the hardware elements to make them amenable to software analysis, reasoning, validation and development. So I’m out to create an ADL (or extend an existing one) that supports hardware analysis, reasoning and validation/development support, and see if an end-user tool based on such an ADL is deemed actually useful by electronics experts.
This is my first research project since my MSc thesis nearly a decade ago (though this one’s not as demanding) and am really looking forward to it. The project is expected to run over the next 10 months or so. I’ll post sporadic progress notes here and point to published products when they become available.